/*
 * Copyright (c) 2009-2010 HIT Microelectronic Center
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *
 * Authors: Gou Pengfei
 *          Jin Yinghan
 *
 * Date: Dec. 2009
 *       Dec. 2010
 *
 */

#ifndef __CPU_EDGE_MEM_DEP_UNIT_HH__
#define __CPU_EDGE_MEM_DEP_UNIT_HH__

#include <list>
#include <set>
#include <map>

#include "base/hashmap.hh"
#include "base/refcnt.hh"
#include "base/statistics.hh"
#include "cpu/inst_seq.hh"

class DerivEdgeCPUParams;

/**
 * @todo: In EDGE model, memory dependence is maintianed in an extremely conservative
 * way right now that all loads most wait util its prior stores executed. This is really
 * inefficient to detailly model EDGE. Fix this!
 */
template <class MemDepPred, class Impl>
class EdgeMemDepUnit
{
  protected:
    std::string _name;

  public:
    typedef typename Impl::DynInstPtr DynInstPtr;

    typedef typename Impl::CPUPol CPUPol;
    typedef typename CPUPol::IQ IQ;

    /** Empty constructor. Must call init() prior to using in this case. */
    EdgeMemDepUnit();

    /** Constructs a EdgeMemDepUnit with given parameters. */
    EdgeMemDepUnit(DerivEdgeCPUParams *params);

    /** Frees up any memory allocated. */
    ~EdgeMemDepUnit();

    /** Returns the name of the memory dependence unit. */
    std::string name() const { return _name; }

    /** Initializes the unit with parameters and a thread id. */
    void init(DerivEdgeCPUParams *params, ThreadID tid);

    /** Registers statistics. */
    void regStats();

    /** Switches out the memory dependence predictor. */
    void switchOut();

    /** Takes over from another CPU's thread. */
    void takeOverFrom();

    /** Sets the pointer to the IQ. */
    void setIQ(IQ *iq_ptr);

    /** Inserts a memory instruction. */
    void insert(DynInstPtr &inst);

    /** Inserts a non-speculative memory instruction. */
    void insertNonSpec(DynInstPtr &inst);

    /** Inserts a barrier instruction. */
    void insertBarrier(DynInstPtr &barr_inst);

    /** Indicate that an instruction has its registers ready. */
    void opsReady(DynInstPtr &inst);

    /** Indicate that a non-speculative instruction is ready. */
    void nonSpecInstReady(DynInstPtr &inst);

    /** Reschedules an instruction to be re-executed. */
    void reschedule(DynInstPtr &inst);

    /** Replays all instructions that have been rescheduled by moving them to
     *  the ready list.
     */
    void replay();

    /** Completes a memory instruction. */
    void completed(DynInstPtr &inst);

    /** Completes a barrier instruction. */
    void completeBarrier(DynInstPtr &inst);

    /** Wakes any dependents of a memory instruction. */
    void wakeDependents(DynInstPtr &inst);

    /** Squashes all instructions up until a given sequence number for a
     *  specific thread.
     */
    void squash(const TheISA::BlockID &squashed_num, ThreadID tid);

    /** Indicates an ordering violation between a store and a younger load. */
    void violation(DynInstPtr &store_inst, DynInstPtr &violating_load);

    /** Issues the given instruction */
    void issue(DynInstPtr &inst);

    /** Debugging function to dump the lists of instructions. */
    void dumpLists();

    /** 
     * Find the last store inst prior to a specific mem ref inst.
     * This is a conservative way to guarantee mem dependence
     * that every mem ref inst should have waited until the prior last
     * store inst finished.
     * */
    int64_t findLastStore(DynInstPtr &inst, ThreadID tid);

    /**
     * Find all the last stores prior to this memory ref inst.
     * */
    void findLastStores(DynInstPtr &inst, std::vector<uint64_t> &result, ThreadID tid);

    /** 
     * Check dependence of a load to a store. I assume this
     * function can only be invoked in Perfect-Mem-Dep-Mode. 
     * */
    bool checkDependent(DynInstPtr &load_inst, DynInstPtr &store_inst);

  private:
    typedef typename std::list<DynInstPtr>::iterator ListIt;

    class MemDepEntry;

    typedef RefCountingPtr<MemDepEntry> MemDepEntryPtr;

    /** Memory dependence entries that track memory operations, marking
     *  when the instruction is ready to execute and what instructions depend
     *  upon it.
     */
    class MemDepEntry : public RefCounted {
      public:
        /** Constructs a memory dependence entry. */
        MemDepEntry(DynInstPtr &new_inst)
            : inst(new_inst),
            loadDepCount(0), 
            opsReady(false),
            memDepReady(false),
            completed(false),
            squashed(false),
            issued(false)
        {
#ifdef DEBUG
            ++memdep_count;

            DPRINTF(EdgeMemDepUnit, "Memory dependency entry created.  "
                    "memdep_count=%i\n", memdep_count);
#endif
        }

        /** Frees any pointers. */
        ~MemDepEntry()
        {
            for (int i = 0; i < dependInsts.size(); ++i) {
                dependInsts[i] = NULL;
            }

        // Bug of m5 for not adding this?
        //inst = NULL;

#ifdef DEBUG
            --memdep_count;

            DPRINTF(EdgeMemDepUnit, "Memory dependency entry deleted.  "
                    "memdep_count=%i\n", memdep_count);
#endif
        }

        /** Returns the name of the memory dependence entry. */
        std::string name() const { return "memdepentry"; }

        /** The instruction being tracked. */
        DynInstPtr inst;

        /** The iterator to the instruction's location inside the list. */
        ListIt listIt;

        /** A vector of any dependent instructions. */
        std::vector<MemDepEntryPtr> dependInsts;

        /** 
         * Load insts may be dependent on multiple stores. Only after
         * all the dependent stores are executed, load can be ready to
         * issue. 
         * */
        int loadDepCount;

        /** If the operands are ready or not. */
        bool opsReady;
        /** If all memory dependencies have been satisfied. */
        bool memDepReady;
        /** If the instruction is completed. */
        bool completed;
        /** If the instruction is squashed. */
        bool squashed;
        /** If the instruction has been issued in mem dep unit. */
        bool issued;

        /** For debugging. */
#ifdef DEBUG
        static int memdep_count;
        static int memdep_insert;
        static int memdep_erase;
#endif
    };

    /** Finds the memory dependence entry in the hash map. */
    inline MemDepEntryPtr findInHash(const DynInstPtr &inst);

    /** Moves an entry to the ready list. */
    inline void moveToReady(MemDepEntryPtr &ready_inst_entry);

    typedef std::multimap<uint64_t, MemDepEntryPtr> MemDepHash;

    typedef typename MemDepHash::iterator MemDepHashIt;

    MemDepHash memDepHash;

    /** A list of all instructions in the memory dependence unit. */
    std::list<DynInstPtr> instList[Impl::MaxThreads];

    /** A list of all instructions that are going to be replayed. */
    std::list<DynInstPtr> instsToReplay;

    /** Is there an outstanding load barrier that loads must wait on. */
    bool loadBarrier;
    /** The sequence number of the load barrier. */
    InstSeqNum loadBarrierSN;
    /** Is there an outstanding store barrier that loads must wait on. */
    bool storeBarrier;
    /** The sequence number of the store barrier. */
    InstSeqNum storeBarrierSN;

    /** Pointer to the IQ. */
    IQ * iqPtr;

    /** The thread id of this memory dependence unit. */
    int id;

    /** Perfect mode flag. */
    bool isPerfect;

    /** Stat for number of inserted loads. */
    Stats::Scalar insertedLoads;
    /** Stat for number of inserted stores. */
    Stats::Scalar insertedStores;
    /** Stat for number of conflicting loads that had to wait for a store. */
    Stats::Scalar conflictingLoads;
    /** Stat for number of conflicting stores that had to wait for a store. */
    Stats::Scalar conflictingStores;
};

#endif // __CPU_EDGE_MEM_DEP_UNIT_HH__
